A digital-controlled phase locked loop circuit (DPLL circuit) generates and outputs a clock signal POUT by multiplying the frequency of a reference clock signal PREF, for example, as disclosed in U.S. Pat. No. 5,517,155 (JP 7-283722A) and U.S. Pat. No. 5,708,395 (JP 8-265111A).
In U.S. Pat. No. 5,517,155, as shown in FIG. 6, a DPLL circuit 100 multiplies the frequency of a reference signal PREF that is input from an external circuit according to divisor data DV1 to DV10 of 10 bits representative of multiplication number to generate an output signal POUT The DPLL circuit starts outputting the output signal POUT upon receiving an operation start signal PSTB from the external circuit. Upon inputting a control signal PA of high level from the external circuit, a ring oscillator 42 outputs 16 multiphase clocks R1 to R16 having a given phase difference Tg. A pulse phase difference encoder circuit 44 encodes a period of an internal clock PB that is an ORed signal of a frequency-divided signal BOW produced by dividing the frequency of the output signal POUT by the multiplication number and the reference signal PREF by the multiphase clocks R1 to R16, which are output from the ring oscillator 42. The pulse phase difference encoder circuit 44 generates binary digital data DD1 to DD18 and DE1 to DE18 of 16 bits corresponding to the period of the reference signal PREF and a phase difference between the reference signal PREF and the frequency-divided signal BOW.
Also, a data control circuit 46 generates control data DM1 to DM19 of 19 bits for controlling the phase difference between the reference signal PREF and the output signal POUT to ½ of the period of the reference signal PREF on the basis of the data DD and DE. A divider 48 divides the control data DM by the divisor data DV1 to DV10 that is input from the external circuit. The divider 48 outputs the higher significant bit data DQ1 to DQ18 of 18 bits which are representative of divided values larger than 0 (decimal point) and the lower significant bit data DP1 to DP10 of 10 bits which are representative of divided values smaller than 0 (decimal point) as the division results, separately.
A data distributor circuit 50 outputs a select signal CDS that changes in the level at frequencies corresponding to the data DP, and outputs the frequency-divided signal BOW at a timing at which the output signal POUT is divided in the frequency by the divisor data DV. The data distributor circuit 50 further outputs a timing signal DLS representative of the latch timing of the data to a data latch circuit 52 at a subsequent stage. The data latch circuit 52 receives the select signal CDS and the timing signal DLS, and latches the higher significant bit data DQ that is output from the divider 48 when the timing signal DLS becomes high. Also, the data latch circuit 52 outputs the latch data DQ or data DQ+1 produced by adding “1” to the latch data DQ according to the select signal CDS, as the frequency control data CD1 to CD18 of 18 bits which is representative of the period of the output signal POUT A digital control oscillator circuit (DCO) 54 generates the output signal POUT of a period corresponding to the frequency control data CD from the data latch circuit 52 by using the multiphase clocks R1 to R16 that are output from the ring oscillator 42. A PLL operation control circuit 56 controls the operation timing of the respective circuits.
Specifically, the digital control oscillator circuit 54 sets the higher significant side data of the frequency control data CD in an internal down-counter, and counts down the data on the basis of a high-speed clock signal of the ring oscillator 42, to thereby produce the period of the frequency-multiplied clock signal POUT The frequency-multiplied clock signal POUT of the DPLL circuit 100 is supplied to a digital circuit such as a microcomputer as an operation clock signal.
In the above system, when the processing speed of the digital circuit is increased, the clock frequency of the ring oscillator 42 that is incorporated into the DPLL circuit 100 is made higher. The frequency has been about 100 MHz up to now, but reaches the GHz order in recent years. As a result, the down-counter within the digital control oscillator circuit 54 is required to conduct the count-down operation according to a higher-speed clock signal.
However, in general, the counter needs to more increase the margin of a time (operation margin) required for digit-up or digit-down as the number of digits is more increased. Accordingly, when only the ring oscillator 42 portion of the digital control oscillator circuit 54 is improved, and the down-counter portion is maintained as it is, the operation margin of the counter is reduced as much as the frequency of the count clock signal is increased.
In addition, taking a process variation in a semiconductor device, a variation in a supply voltage or a temperature, or a frequency variation in the reference clock signal PREF into consideration, the operation margin of the counter is further decreased. Thus, when data large in the number of digits is set, the count operation of the down-counter is not ensured. As a result, what value the frequency of the frequency-multiplied clock signal POUT becomes is unclear, and the operation of the digital circuit to which the clock signal is supplied is not also ensured.